NXP Semiconductors - Full Speed - DFU Driver

32-bit ARM Cortex-M4 microcontroller; 360 kB SRAM; High-speed USB device/host + PHY; Full-speed USB device/host; Ethernet AVB; LCD; EMC; SPIFI; CAN FD, SDIO; 12-bit 5 Msamples/s ADC; DMIC subsystem

The is a family of ARM Cortex-M4 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption and enhanced debug features. The ARM a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated into the core. The LPC540xx family includes KB of on-chip SRAM, a quad SPI Flash Interface (SPIFI) for expanding program memory, one high-speed and one full-speed USB host and device controller, Ethernet AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory Controller (EMC), a DMIC subsystem with PDM microphone interface and I2S, five general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals (USART, SPI, I2S, I2C interface), Secure Hash Algorithm (SHA), 12-bit 5.0 Msamples/sec ADC, and a temperature sensor.

ARM Cortex-M4 core (version r0p1): ARM Cortex-M4 processor, running at a frequency to 180 MHz. Floating Point Unit (FPU) and Memory Protection Unit (MPU). ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC). Non-maskable Interrupt (NMI) input with a selection of sources. Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watch points. Includes Serial Wire Output and ETM Trace for enhanced debug capabilities, and a debug timestamp counter. System tick timer. On-chip memory: 360 KB total SRAM consisting 160 KB contiguous main SRAM and an additional 192 KB SRAM on the I&D buses. KB of SRAM bank intended for USB traffic.

General-purpose One-Time Programmable (OTP) memory for user application specific data ROM API support: In-Application Programming (IAP) and In-System Programming (ISP). ROM-based USB drivers (HID, CDC, MSC, and DFU). Supports serial interface booting (UART, I2C, SPI) from an application processor, automated booting from NOR flash (quad SPIFI, 8/16/32-bit external parallel flash), and USB booting (full-speed, high-speed). Execute in place (XIP) from SPIFI NOR flash (in quad, dual SPIFI mode or single-bit SPI mode), and parallel NOR flash. FRO API for selecting FRO output frequency. OTP API for programming OTP memory. Random Number Generator (RNG) API. Serial interfaces: Flexcomm Interface contains to 11 serial peripherals. Each Flexcomm Interface (except flexcomm 10, which is dedicated for SPI) can be selected by software be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A variety of clocking options are available to each Flexcomm Interface and include a shared fractional baud-rate generator. I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave. Two ISO 7816 Smart Card Interfaces with DMA support. USB 2.0 high-speed host/device controller with on-chip high-speed PHY. USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode using software library. See Technical note TN00033 for more details. SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI flash memory at a much higher rate than standard SPI or SSP interfaces. Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and dedicated DMA controller. Two CAN FD modules with dedicated DMA controller. Digital peripherals: DMA controller with 32 channels and to 24 programmable triggers, able to access all memories and DMA-capable peripherals. LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film Transistor (TFT) displays. It has a dedicated DMA controller, selectable display resolution (up x 768 pixels), and supports to 24-bit true-color mode. External Memory Controller (EMC) provides support for asynchronous static memory devices such as RAM, ROM and flash, in addition to dynamic memories such as single data rate SDRAM with an SDRAM clock to 100 MHz. EMC bus width (bit) TFBGA180, TFBGA100, and LQFP100 packages supports to 8/16 data line wide static memory. Secured digital input/output (SD/MMC and SDIO) card interface with DMA support. CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support.

LPC540xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.

to 171 General-Purpose Input/Output (GPIO) pins. GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports. Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising, falling or both input edges. Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states. Analog peripherals: 12-bit ADC with 12 input channels and with multiple internal and external trigger inputs and sample rates to 5.0 MSamples/sec. The ADC supports two independent conversion sequences. Integrated temperature sensor connected to the ADC. DMIC subsystem includes a dual-channel PDM microphone interface with decimators, filtering, and hardware voice activity detection. The processed output data can be routed directly an I2S interface if needed. Timers: Five 32-bit general purpose timers/counters. All five timers support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests. One SCTimer/PWM with eight input and ten output functions (including capture and match). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16 events, and 16 states. 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. A timer in the RTC can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution. Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation up to four programmable, fixed rates. Windowed Watchdog Timer (WWDT). Repetitive Interrupt Timer (RIT) for debug time stamping and for general purpose use. Security features: Secure Hash Algorithm (SHA1/SHA2) module supports boot with dedicated DMA controller. Clock generation: 12 MHz internal Free Running Oscillator (FRO). This oscillator provides a selectable 48 MHz or 96 MHz output, and a 12 MHz output (divided down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed 1 % accuracy over the entire voltage and temperature range. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz. 32.768 kHz low-power RTC oscillator. System PLL allows CPU operation up to the maximum CPU rate and can run from the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHz RTC oscillator. Two additional PLLs for USB clock and audio subsystem. Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.

All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.

Based on the highly energy-efficient Arm® Cortex®-M0+ core and operating at CPU frequencies of up to 100 MHz, NXP’s 32-bit LPC51U68 microcontrollers for embedded applications feature larger

NXP Semiconductors offers two power blocks that promise to expand the RF power industry and become a standard for years to come. The simplicity of these LDMOS transistors lies in the joint availability